A statistical-based scheduling algorithm in automated data path synthesis

In this paper, we propose a new heuristic scheduling algorithm based on the statistical analysis of the cumulative frequency distribution of operations among control steps. It has a tendency of escaping from local minima and therefore reaching a globally optimal solution. The presented algorithm considers the real world constraints such as chained operations, multicycle operations, and pipelined data paths. The result of the experiment shows that it gives optimal solutions, even though it is greedy in nature

High accuracy EEG biometrics identification using ICA and AR model

Modern biometric identification methods combine interdisciplinary approaches to enhance person identification and classification accuracy. One popular technique for this purpose is Brain-Computer Interface (BCI).The signal so obtained from BCI will be further processed by the Autoregressive (AR) Model for feature extraction. Many researches in the area find that for more accurate results, the signal must be cleaned before extracting any useful feature information. This study proposes Independent Component Analysis (ICA), k-NN classifier, and AR as the combined techniques for electroencephalogram (EEG) biometrics to achieve the highest personal identification and classification accuracy. However, there is a classification gap between using the combined ICA with the AR model and AR model alone.Therefore, this study takes one step further by modifying the feature extraction of AR and comparing the outcome with the proposed approaches in lieu of prior researches. The experiment based on four relevant locations shows that the combined ICA and AR can achieve higher accuracy than the modified AR. More combinations of channels and subjects are required in future research to explore the significance of channel effects and to enhance the identification accuracy

Methods for Cell Compilation With Constraints (Vlsi, Pla, Routing, Silicon)

141 p.Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 1986.One method in solving the VLSI layout problems is a library of standard cells which are used as standard building blocks. Therefore, the design problem is partitioned into two subproblems: (a) decomposition of design into standard cells and (b) placement and routing of standard cells used in the design. The first problem of standard-cell methodology is that library has to be maintained and updated because each cell is usually needed in many different versions. All of them have the same functionality but slightly different in electrical charateristics (time delay, power consumption), geometrical characteristics (height, width) and the position of each input/output. The solution to this problem is a library of parametrized cells.The second problem with standard cell approach is the extensive area of the chip used by routing. We lay very dense cells and then lose all that gain by extensive routing between the cells. Through-the-cell routing provides the solution.This dissertation introduces a new direction of layout design based on PLA structure and, also, proposed new and practical solutions to the problems of this new direction. The dissertation discusses the problems of cell compilation with constraints and proposes the practical algorithms for those problems. The main constraints are (1) 4-directional I/O. Any I/O can be specified on the boundary of the cell at any given position in the term of lambda. The compilier is able to handle multi-terminal nets. (2) Through-the-cell Routing. All routes are superimposed on a cell. Routing information is considered to be a part of the functional description. (3) Resizable Device. The entire cell is decomposed symbolically into subcells called parametrized layout macros such as contact, transistor. Each layout macro can be sized according to its delay time and power consumption. (4) No Limitation of Number of Logic Levels. The cell description is able to describe more than two levels (AND-OR) of logic. (5) Pass-transistor term description is included in the language so that precharge, high impedance and dynamic register can be practically implemented in the layout by the designer.The layout architecture is based on a PLA structure with two layers of metal and one layer of polysilicon and diffusion. The proposed structure of PLA in this dissertation is different from other conventional PLA structures as follows: (1) AND and OR planes are not physically separated but interleaved. (2) Folding is performed by clustering all variables together according to their weights. The weight of any variable depends on the number of terms having that variable. (3) Pull-up transistors are folded by moving them into the unused holes inside a cell. (4) Routing is considered as a part of term layout and is processed simultaneously with the term layout.U of I OnlyRestricted to the U of I community idenfinitely during batch ingest of legacy ETD

Enhancing Mean-Variance Mapping Optimization Using Opposite Gradient Method and Interior Point Method for Real Parameter Optimization Problems

The aim of optimization methods is to identify the best results in the search area. In this research, we focused on a mixture of the interior point method, opposite gradient method, and mean-variance mapping optimization, named IPOG-MVMO, where the solutions can be obtained from the gradient field of the cost function on the constraint manifold. The process was divided into three main phases. In the first phase, the interior point method was applied for local searching. Secondly, the opposite gradient method was used to generate a population of candidate solutions. The last phase involved updating the population according to the mean and variance of the solutions. In the experiments on real parameter optimization problems, three types of functions, which were unimodal, multimodal, and continuous composition functions, were considered and used to compare our proposed method with other meta-heuristics techniques. The results showed that our proposed algorithms outperformed other algorithms in terms of finding the optimal solution

Extracting Salient Visual Attention Regions by Color Contrast and Wavelet Transformation

Abstract—Visual attention detection is an important technique in many computer vision applications. In this paper, we propose an algorithm to extract a salient object from an image using bottom-up and top-down computations. In bottomup computation, segment-based color contrast and attention values are employed to compose a bottom-up saliency map. In top-down computation, in-focus areas of the image are extracted to derive attention values using wavelet transforms for constructing a segment-based top-down saliency map. Attention values from both maps are combined by linear combination. The foreground/background-based salient object extraction is applied to form an output object. Experiments on 1,200 color images show that the proposed algorithm yields high level of satisfaction. I